A brief panorama of the prior art concerning the techniques of simulating a generic communication node model included in a complex system model is set out below.
It will be recalled that a communication node is an essential constituent of current hardware platforms. The bus is the best known type of node and mostly used for interconnecting processors, memories and peripheral components. Bridges and routers are more complex components that we include in the category of communication nodes. In systems integrated on silicon (SoC, for “System on Chip”), the use of interconnection networks (NoC, for “Network on Chip”) is found more and more for remedying the limitations of buses.
In order to illustrates the interest of techniques of simulating a generic communication node model, we will consider, in relation to FIG. 1, a simple electronic system architecture composed of two processors, Proc1 and Proc2, and a common memory 1, interconnected by a bus 2. A set of tasks is executed by each processor (tasks T1 and T2 for the processor Proc1, tasks T3 and T4 for the processor Proc2). More specific hardware functions such as a direct memory access module (DMA, for “Direct Memory Access”) can also exist (module DMA1 for the processor Proc2). The hardware tasks and/or functions exchange data with each other or with the memory by means of the bus. Thus the bus is a critical shared resource that must be managed according to an access policy. The performance properties of the complete system are then very dependent on the behavior of the bus.
This electronic system can be represented by an abstract model given in FIG. 2. The bus is represented by a communication node 20.
FIGS. 3a, 3b and 3c explain the essential difference between three possible abstraction levels for the simulation of exchanges provided by the bus. We will consider two exchanges arising simultaneously: Tr1 between T2 (Proc1) and the memory, Tr2 between DMA1 (Proc2) and the memory. The two exchanges will use the common bus according to the access policy defined with the essential characteristic for this bus that only one exchange can take place at any one time. Some policies such as interleaving allow alternation between the two exchanges giving an impression of simultaneity.
FIG. 3a illustrates the “transactional” level (or TA, for “Transaction Accurate”), which is the most abstract level. Each exchange is modeled by an atomic transaction. Thus, transaction Tr1 being underway, transaction Tr2 must await the end of transaction Tr1 in order to have the bus available.
FIG. 3b illustrates the “bus transfer” level (or BA, for “Bus Accurate”) which is a more detailed level. Each exchange is broken down into a frame or packet of fixed length (except for the last one); “burst” is also spoken of. An interleaving between the two exchanges is then possible, for example by alternating allocation of the bus for a packet of each transaction. In the example, and this is general, it is important to note that the times of the end of the transactions Tr1 and Tr2 differ with respect to those of the transactional level. This implies that the entire simulation that follows differs. Thus the two simulations at the levels TA and BA are not equivalent.
FIG. 3c illustrates the “clock cycle” level (or CA, for “Cycle Accurate”), which is the most detailed level. Each exchange is broken down into a series of clock cycles. Each packet is transmitted as a series of elementary words. Each word requires one or more clock cycles. The first word may require several supplementary access cycles (latency time). A correct temporal parameterising of a model of the level BA may give results similar to its corresponding model CA.
The majority of current solutions for simulating electronic systems including hardware and software come within the category of virtual platforms (first known technique). A virtual platform is a simulation model in which the processors are represented by behavioral models based on the instructions of these processors (or ISS, for “Instruction-Set Simulator”), and the buses, the interconnection networks and the memories are modeled by precise models at the exchange cycle or clock cycle. These models make it possible to have simulation results whose precision is around 95% and 99% with respect to the corresponding real solution. The simulation performance is then situated between 100 K instructions and 5 M instructions according to the technique. The performance is better for BA models but also require the use of ISS models.
Transactional simulation (second known technique) is progressively being used, in particular from the standardization of TLM (“Transaction Level Monitoring”), by the OSCI group (Open SystemC Initiative). The transactional simulation known at the present time (hereinafter referred to as “conventional transactional simulation”) considers that each transaction is atomic and therefore does not consider the sharing of a resource such as a bus during simultaneous transactions. The inventor of the present application has no knowledge of existing transactional simulation solutions ensuring the sharing of a bus or interconnection network during simultaneous transactions.
The virtual platform technique (first known technique) has two major drawbacks:                its cost of implementation. This is because it makes it necessary to have available (and therefore purchase or develop) models of processors, buses and memories. It also requires being fairly advanced in the development of the product including the software part since the source software code must be compiled for each target processor to allow its execution by its ISS model. The results obtained, even if they are very precise, arrive very late in the development process, especially well after all the decisions have been taken. The results are said to be of a confirmative nature in contradistinction to prospective results sought by system architects;        the duration of simulation. With the increase in complexity, the simulation times become prohibitive, in particular during the initial phases of exploration of the potential architecture, when it is a case of making a maximum number of iterations for making decisions correctly. Acceleration factors of 100 to 10,000 are required, which can be achieved only by transactional simulation.        
The conventional transactional simulation technique (second known technique) makes it possible to mitigate the aforementioned two drawbacks of the virtual platform technique, by virtue of the following characteristics: use of generic models of components, models of software tasks and hardware functions described in SystemC, acceleration factor of the simulation of 1000 to 10000 with respect to models of the clock cycle level.
However, the conventional transactional simulation technique does not provide precise results since the atomic exchanges introduce significant temporal distortions. The influence of these distortions is greater or lesser according to the fields of application. The systems in the telecommunications and multimedia field are very demanding on the use of resources of the bus, network and memory type, with high real-time constraints. Thus the performance evaluated may prove to be very erroneous.